1. Field of the Invention
The present invention relates to a complex film controlled in its work function at the interface with a substrate under layer, which is applicable for a gate electrode of an MOS transistor and a contact-hole of an interconnect structure of a semiconductor device, and a formation method thereof; and an MOS transistor and an interconnect structure using the complex film and fabrication methods thereof.
2. Description of the Related Art
In a semiconductor device, an SOI (Silicon on Insulator) has been used to simplify the perfect separation between semiconductor elements and to suppress soft error and the latch-up phenomenon inherent to a CMOS transistor. In the relatively early days, an SOI structure having a silicon active layer of about 500 nm in thickness had been examined to increase the speed and reliability of an LSI of CMOS transistors. Recently, it has been known that, by depleting the entire silicon active layer formed on the surface of an SOI by means of thinning the silicon active layer to about 100 nm and controlling the concentration of impurities in a channel region to be relatively low, there can be obtained an excellent semiconductor element capable of suppressing the short-channel effect and improving the current drive ability of an MOS transistor.
However, in an n-type MOS transistor using the general n.sup.+ -polysilicon as a gate electrode material, the concentration of impurities in the channel region must be increased to be about 10.sup.17 /cm.sup.2 or more to ensure the threshold voltage V.sub.th at about 0.5-1.0 V (which is the value for the usual enhancement transistor). Consequently, from the viewpoint of the threshold voltage V.sub.th, it becomes difficult to form a channel region having a relatively low concentration of impurities.
For this reason, in recent years, an examination has been made to use a p.sup.+ -polysilicon (B-DOPOS) doped with boron as a gate electrode material. In this case, a channel region having a sufficiently low concentration of impurities is formed, and thereby a perfect depletion type transistor can be fabricated. The threshold voltage V.sub.th of this perfect depletion type transistor becomes a specified value which is not dependent on the thickness of a silicon active layer of an SOI; however, this value is as high as about 1.0 V for a future LSI aiming at the low power voltage, thereby limiting the design for semiconductors.
In view of the foregoing, it is desirable for the design of the future fine semiconductor elements to control the threshold voltage V.sub.th by controlling the work function at the interface between the gate electrode of an MOS transistor and the backing silicon layer.
On the other hand, in an interconnect structure of a semiconductor device, a large number of contact-holes are formed. The contact-hole is provided on an insulating interlayer formed on an impurity diffusion region (source/drain region) to connect the impurity diffusion region to an upper interconnect layer. Specifically, an insulating interlayer is formed on a silicon semiconductor substrate formed with an impurity diffusion region and an opening is provided in the insulating interlayer, after which a metallization material is deposited in the opening and on the insulating interlayer, thus forming a contact-hole in which the metallization material is embedded in the opening. The metallization material deposited on the insulating interlayer is patterned in a desired pattern, to thus form the upper interconnect layer.
In such a contact-hole, the work function at the interface between the contact-hole at the bottom portion of the opening and the silicon semiconductor substrate is dependent on the metallization material used. Namely, the contact resistance is determined by the work function of the metallization material and the concentration of impurities in the impurity diffusion region.
In a CMOS transistor element, the contact-hole must be formed on an n.sup.+ -Si for an n-type MOS transistor, and on p.sup.+ -Si for a p-type MOS transistor. However, in the case of using the same metallization material contacted with the n.sup.+ -Si and p.sup.+ -Si, it becomes impossible to simultaneously lower the barrier heights in an energy band diagram for the n.sup.+ -Si and p.sup.+ -Si. In the case of using a polysilicon replaced with the metallization material, it becomes possible to simultaneously lower the barrier heights for the n.sup.+ -Si and p.sup.+ -Si. However, the resistance of polysilicon itself is difficult to be lowered, and therefore, for an LSI required for a fine structure, polysilicon is not suitable to be used as the interconnecting material for the contact-hole.
Moreover, a serious problem is the increase in the contact resistance in the contact-hole, that is, an increase in the contact resistance between the metallization material forming the contact hole and the source/drain region. By uniformly reducing elements forming a semiconductor device to be 1/S, the integration is improved to be S.sup.2 times without any change in the chip area and power consumption; however, at the same time, the contact resistance having a constant resistivity is also increased to be S.sup.2 times. The reduction in the contact resistance, therefore, is an inevitable subject for achieving high fineness and high integration of a semiconductor device.
The contact resistivity .rho..sub.c between n.sup.+ silicon and a metal as a metallization material is expressed by the following equation: EQU .rho..sub.c =exp(C.sub.2 .multidot..phi..sub.bn .sqroot.N.sub.d)(1)
where EQU C.sub.2 =.pi..sqroot.(m.sub.n .multidot..epsilon..sub.s)/h
In the above equation, .phi..sub.bn is a barrier height in an energy band diagram which is generally determined between the concentration of n-type impurities in silicon and a metal; .sqroot.N.sub.d is the donor concentration in silicon; m.sub.n is the effective mass of an electron; and .epsilon..sub.s is a permeability of silicon.
As the process temperature in a process of fabricating a semiconductor device has been lowered, it has become difficult to obtain a desired concentration or activity ratio of impurities in silicon. Moreover, as is apparent from the equation (1), the barrier height .phi..sub.bn is present as the first power in the exponent term, so that the effect of the barrier height .phi..sub.bn exerted on the contact resistivity .rho..sub.c is very large. On the other hand, when a metal as a metallization material is determined, the band gap E.sub.g of a semiconductor silicon is expressed by the following equation: EQU E.sub.g =q(.phi..sub.bn +.phi..sub.bp)
where .phi..sub.bp is a barrier height generally determined between the concentration of p-type impurities in silicon and the metal; and q is an elementary quantity of electric charge. PA1 (a) an island-like region formed on a substrate; and PA1 (b) a thin film formed of a material different from that of the island-like region for covering the substrate and the island-like region, PA1 wherein a work function between the substrate and the complex film is controlled by adjusting the area of the island-like region per unit area of the substrate. PA1 (a) a process of forming an island-like region on a substrate while controlling the covering area of the island-like region per unit area of a substrate; and PA1 (b) a process of covering the substrate and the island-like region with a thin film made of a material different from that of the island-like region; PA1 wherein a work function at the interface between the substrate and the complex film by adjusting the area of the island-like region per unit area of the substrate. PA1 (a) a process of forming a source/drain region on a silicon semiconductor substrate, forming an insulating layer over the whole surface, and forming an opening in the insulating layer over the source/drain region; PA1 (b) a process of forming a metal layer at least in the opening, and implanting ions of an impurity having the same conducting type as that of the source/drain region in the metal layer; PA1 (c) a process of heating the silicon semiconductor substrate for allowing the metal forming the metal layer on the bottom portion of the opening to react with silicon forming the silicon semiconductor substrate thereby forming a metal silicide layer on the bottom portion of the opening, precipitating silicon crystal grains in the metal silicide layer at and near the interface with the source/drain region on the bottom portion of the opening, and activating the impurity implanted and entrapped in the precipitated silicon crystal grains; and PA1 (d) a process of depositing a metallization material at least in the opening. PA1 (a) a process of forming a source/drain region on a substrate, forming an insulating layer over the whole surface, and forming an opening in the insulating layer over the source/drain region; PA1 (b) a process of forming a metal silicide layer rich in silicon at least in the opening, and implanting ions of an impurity having the same conducting type as that of the source/drain region in the metal silicide layer; PA1 (c) heating the substrate for precipitating silicon crystal grains in the metal silicide layer at and near the interface with the source/drain region on the bottom portion of the opening, and activating the impurity implanted and entrapped in the precipitated silicon crystal grains; and PA1 (d) a process of depositing a metallization material at least in the opening. PA1 a metal silicide layer formed at least on the bottom portion; and PA1 a metallization material formed on the metal silicide layer; PA1 wherein silicon crystal grains containing to a large extent an impurity having the same conducting type as that of the source/drain region are formed in the metal silicide layer at and near the interface with the source/drain region.
Accordingly, as the value .phi..sub.bn for the n-type semiconductor silicon is reduced, the value .phi..sub.bp for the p-type semiconductor silicon is increased; and vice versa. Therefore, it is impossible to simultaneously reduce the values .phi..sub.bn and .phi..sub.bp. In other words, in a complementary MOS transistor (CMOS) having n-type and p-type channel MOS transistors, it is impossible to simultaneously reduce the contact resistances of the n-type channel and the p-type channel MOS transistors using one kind of a metallization material.
It becomes possible to simultaneously reduce the contact resistances of the n-type and p-type channel MOS transistors using different metallization materials for the contact-holes of the n-type and p-type channel MOS transistors; however, this method presents a problem in significantly complicating the fabricating process for the CMOS transistor.
A technique of fabricating gate electrodes of an n-type and p-type channel MOS transistor elements has been known in "LIGHTLY IMPURITY DOPED (LD) Mo SILICIDE GATE TECHNOLOGY", MASAKAZU KAKUMU, et al., Abstract of IEDM, pp. 415 (15.5), 1985!. The technique involves forming a gate oxide; forming a molybdenum silicide layer rich in silicon by sputtering; implanting ions of arsenic in a region, on which a n-type channel MOS transistor element is to be formed, of the molybdenum silicide layer; implanting ions of boron in a region, on which a p-type channel MOS transistor element is to be formed, of a molybdenum silicide layer; and patterning the molybdenum silicide layer. In this document, it is reported that silicon atoms are precipitated on the molybdenum silicide layer near the interface between the molybdenum silicide layer and the gate oxide film after the heating process. Moreover, there appears the description that the work function .phi..sub.m of the molybdenum silicide forming the gate electrode can be accurately controlled by the amount of the implanted ions. However, there is no description regarding the reduction in the resistance of the contact-hole, particularly the reduction in the contact-holes formed on an n-type and p-type channel MOS transistor elements in a CMOS transistor.